1. Field of the Invention
This invention relates to the process of verifying timing constraints in an integrated circuit. More specifically, this invention relates to the process of reducing timing pessimism during static timing analysis.
2. Related Art
Rapid advances in computing technology have made it possible to perform trillions of computational operations each second on data sets that are sometimes as large as trillions of bytes. These advances can be largely attributed to the exponential increase in the size and complexity of integrated circuits.
Due to the increase in size and complexity of integrated circuits, it has become necessary to use sophisticated tools to verify timing constraints.
Before the advent of Static Timing Analysis (STA), timing constraints were typically verified using simulation-based techniques. As the complexity of integrated circuits grew, using simulation-based techniques to verify timing constraints became impractical because of their long runtimes, low capacities, and incomplete analyses.
Unlike simulation-based techniques, STA verifies timing by computing the worst-case delays without enumerating all possible paths. Because of this, STA can perform a thorough timing analysis for large integrated circuits within a reasonable amount of time. As a result, STA has emerged as the method of choice for verifying timing constraints for large integrated circuits.
A number of factors must be considered while performing STA. The design and fabrication of integrated circuits involve complex physical and chemical processes, which cause on-chip variation of timing-related parameters. Typically, STA techniques model this on-chip variation using a global derating factor, which is used to change (or derate) delays to reflect on-chip variation. Since a global derating factor is globally applied to every delay, it ignores the context or location where each delay occurs.
Consequently, present STA techniques usually solve for the worst case scenario for on-chip variation, which typically results in a safe but pessimistic timing analysis.
Unfortunately, due to the continuing miniaturization of feature sizes, timing constraints for integrated circuits are becoming increasingly stringent. As a result, it is becoming extremely difficult to design integrated circuits using present STA techniques due to their overly pessimistic timing analyses.
Hence, what is needed is a method and apparatus that reduces timing pessimism during STA without significantly increasing the computational time.